A New Multiplier Using Wallace Structure and Carry Select Adder with Pipelining
نویسنده
چکیده
Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the Wallace tree structure with pipelining. A fast carry select adder is used for the final two-operand adder. It is shown that the time delay for the entire multiplier is O(log(n)). The design is particularly carried out for a 32-bit multiplier with two sections of pipelining, to balance the delays through the multiplier. A total of ten gate delays is all needed for the multiplication throughput. Index Terms – Multiplier, Wallace structure, Carry-select adder, Pipelining.
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